EP3C5E144C8N Datasheet, PDF (40/348 Pages) Altera Corporation – Ability to disable external JTAG port

3–6
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
The address clock enable is typically used to improve the effectiveness of cache
memory applications during a cache-miss. The default value for the address clock
enable signals is low.
Figure 3–4 and Figure 3–5 show the address clock enable waveform during read and
write cycles, respectively.
Figure 3–4. Cyclone III Device Family Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
a0
a1
a2
a3
a4
a5
a6
rden
addressstall
latched address
(inside memory) ^an
a0
a1
a4
a5
q (synch) doutn-1 doutn
dout0
dout1
dout1
dout1
dout4
q (asynch) doutn
dout0
dout1
dout1
dout1
dout4
dout5
Figure 3–5. Cyclone III Device Family Address Clock Enable During Write Cycle Waveform
inclock
wraddress
a0
a1
data
00
01
wren
addressstall
latched address
(inside memory)
an
a0
contents at a0 XX
contents at a1
XX
contents at a2
contents at a3
contents at a4
contents at a5
a2
a3
02
03
a1
00
01
02
XX
XX
XX
XX
a4
a5
a6
04
05
06
a4
a5
03
04
05
Mixed-Width Support
M9K memory blocks support mixed data widths. When using simple dual-port, true
dual-port, or FIFO modes, mixed width support allows you to read and write
different data widths to an M9K memory block. For more information about the
different widths supported per memory mode, refer to “Memory Modes” on
page 3–7.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation