EP3C5E144C8N Datasheet, PDF (304/348 Pages) Altera Corporation – Ability to disable external JTAG port

1–24
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side ⁽¹⁾ (Part 2 of 2)
Memory
Standard
I/O Standard
Column I/Os (ps)
Lead
Lag
Row I/Os (ps)
Lead
Lag
Wraparound Mode (ps)
Lead
Lag
SSTL-18 Class I
DDR2 SDRAM
SSTL-18 Class II
915
410
915
410
1015
510
1025
545
1025
545
1125
645
DDR SDRAM
SSTL-2 Class I
SSTL-2 Class II
880
340
880
340
980
440
1010
380
1010
380
1110
480
1.8 V HSTL Class I
910
450
910
450
1010
550
QDRII SRAM
1.8 V HSTL Class II
1010
570
1010
570
1110
670
C8
SSTL-18 Class I
DDR2 SDRAM
SSTL-18 Class II
1040
440
1040
440
1140
540
1180
600
1180
600
1280
700
DDR SDRAM
SSTL-2 Class I
SSTL-2 Class II
1010
360
1010
360
1110
460
1160
410
1160
410
1260
510
1.8 V HSTL Class I
1040
490
1040
490
1140
590
QDRII SRAM
1.8 V HSTL Class II
1190
630
1190
630
1290
730
I7
SSTL-18 Class I
DDR2 SDRAM
SSTL-18 Class II
961
431
961
431
1061
531
1076
572
1076
572
1176
672
DDR SDRAM
SSTL-2 Class I
SSTL-2 Class II
924
357
924
357
1024
457
1061
399
1061
399
1161
499
1.8 V HSTL Class I
956
473
956
473
1056
573
QDRII SRAM
1.8 V HSTL Class II
1061
599
1061
599
1161
699
A7
DDR2 SDRAM ^{SSTL-18 Class I}
(2)
SSTL-18 Class II
1092
462
1092
462
1192
562
1239
630
1239
630
1339
730
DDR SDRAM
SSTL-2 Class I
SSTL-2 Class II
1061
378
1061
378
1161
478
1218
431
1218
431
1318
531
1.8 V HSTL Class I
1092
515
1092
515
1192
615
QDRII SRAM
1.8 V HSTL Class II
1250
662
1250
662
1350
762
Notes to Table 1–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.
Table 1–34 lists the memory output clock jitter specifications for Cyclone III devices.
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications ^{(1), (2)} (Part 1 of 2)
Parameter
Clock period jitter
Cycle-to-cycle period jitter
Symbol
t_JIT(per)
t_JIT(cc)
Min
Max
Unit
-125
125
ps
-200
200
ps
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation