|
EP3C5E144C8N Datasheet, PDF (190/348 Pages) Altera Corporation – Ability to disable external JTAG port | |||
|
◁ |
9â32
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9â12 shows the recommended balanced star routing for multiple bus master
interfaces to minimize signal integrity issue.
Figure 9â12. Balanced Star Routing
DCLK
Cyclone III
Master Device
M (1)
External
Master Device
N (2)
N (2)
Numonyx Flash
Notes to Figure 9â12:
(1) Altera does not recommend M to exceed six inches as listed in Table 9â12 on page 9â30.
(2) Altera recommends using a balanced star routing. Try to keep the N length equal and as short as possible to minimize
reflection noise from the transmission line. The M length is applicable for this setup.
Estimating the AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to the Cyclone III devices. This parallel interface is clocked by the
Cyclone III DCLK output (generated from an internal oscillator). As listed in Table 9â8
on page 9â14, the DCLK minimum frequency when using the 40-MHz oscillator is
20 MHz (50 ns). In word-wide cascade programming, the DATA[15..0] bus transfers a
16-bit word and essentially cuts configuration time to approximately 1/16 of the AS
configuration time. Therefore, the maximum configuration time estimation for an
EP3C40 device (9,600,000 bits of uncompressed data) is defined in Equation 9â4 and
Equation 9â5.
Equation 9â4.
Size
Ã
ï¦
ï¨
m---1---6a---x-b--i-i-m-t--s--u--p--m--e---r-D---D--C--C--L--L--K--K----p--c-e--y-r--c-i-o-l-e--d--ï¸ï¶
=
estimated maximum configuration ti
Equation 9â5.
9,600,000
bits
Ã
ï¦
ï¨
1--5-6--0---b--n-i--ts--s-ï¸ï¶
=
30 ms
To estimate a typical configuration time, use the typical DCLK period listed in Table 9â8
on page 9â14. With a typical DCLK period of 33.33 ns, the typical configuration time is
20 ms.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
|
▷ |