EP3C5E144C8N Datasheet, PDF (166/348 Pages) Altera Corporation – Ability to disable external JTAG port

9–8
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
All I/O inputs must maintain a maximum AC voltage of 4.1 V. When using a JTAG
configuration scheme or a serial configuration device in an AS configuration scheme,
you must connect a 25-Ω series resistor at the near end of the TDO and TDI pin or the
serial configuration device for the DATA[0]pin. When cascading Cyclone III device
family in a multi-device configuration, you must connect the repeater buffers between
the master and slave devices for DATA and DCLK.
The output resistance of the repeater buffers must fit the maximum overshoot
equation shown in Equation 9–1:
Equation 9–1. ⁽¹⁾
0.8ZO ≤ RE ≤ 1.8ZO
Note to Equation 9–1:
(1) Z_O is the transmission line impedance and R_E is the equivalent resistance of the output buffer.
Configuration Process
This section describes the configuration process.
f For more information about the configuration cycle state machine of Altera^® FPGAs,
refer to the Configuring Altera FPGAs chapter in volume 1 of the Configuration
Handbook.
Power Up
If the device is powered up from the power-down state, the V_CCIO for all the I/O
banks must be powered up to the appropriate level for the device to exit POR.
To begin configuration, the required voltages listed in Table 9–4 must be powered up
to the appropriate voltage levels.
Table 9–4. Power-Up Voltage for Cyclone III Device Family Configuration
Device
Voltage that must be Powered-Up ⁽¹⁾
Cyclone III
Cyclone III LS
V_CCINT, V_CCA, V_CCIO ⁽²⁾
V_CCBAT, V_CCINT, V_CCA, V_CCIO ⁽²⁾
Notes to Table 9–4:
(1) Voltages must be powered up to the appropriate voltage levels to begin configuration.
(2) V_CCIO is for banks in which the configuration and JTAG pins reside.
Reset
When nCONFIG or nSTATUS is low, the device is in reset. After power-up, the Cyclone III
device family goes through POR. POR delay depends on the MSEL pin settings,
which correspond to your configuration scheme.
Depending on the configuration scheme, a fast or standard POR time is available.
POR time for fast POR ranges between 3–9 ms. POR time for standard POR, which
has a lower power-ramp rate, ranges between 50–200 ms.
During POR, the device resets, holds nSTATUS and CONF_DONE low, and tri-states all
user I/O pins.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation