EP3C5E144C8N Datasheet, PDF (338/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–24
Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side ⁽¹⁾ (Part 2 of 2)
Memory Standard
I/O Standard
Column I/Os (ps)
Lead
Lag
Row I/Os (ps)
Lead
Lag
Wraparound Mode (ps)
Lead
Lag
I7
DDR2 SDRAM
SSTL-18 Class I
SSTL-18 Class II
961
431
961
431
1061
531
1076
572
1076
572
1176
672
DDR SDRAM
SSTL-2 Class I
SSTL-2 Class II
924
357
924
357
1024
457
1061
399
1061
399
1161
499
QDRII SRAM
1.8-V HSTL Class I
956
473
956
473
1056
573
1.8-V HSTL Class II
1061
599
1061
599
1161
699
Note to Table 2–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
Table 2–34 lists the Cyclone III LS devices memory ouput clock jitter specifications.
Table 2–34. Cyclone III LS Devices Memory Output Clock Jitter Specifications ^{(1), (2)}
Parameter
Symbol
Min
Max
Unit
Clock period jitter
t_JIT (per)
–125
125
ps
Cycle-to-cycle period jitter
t_JIT (cc)
–200
200
ps
Duty cycle jitter
t_JIT (duty)
–150
150
ps
Notes to Table 2–34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specification
Table 2–35 lists the worst case duty cycle distortion for Cyclone III LS devices.
Table 2–35. Duty Cycle Distortion on Cyclone III LS Devices I/O Pins ^{(1), (2)} (Preliminary)
Symbol
C7, I7
C8
Unit
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
%
Notes to Table 2–35:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and I/O element
(IOE) driving the dedicated and general purpose I/O pins.
(2) Cyclone III LS devices meet the DCD specifications at the maximum output toggle rate for each combination of
the I/O standard and current strength.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation