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EP3C5E144C8N Datasheet, PDF (142/348 Pages) Altera Corporation – Ability to disable external JTAG port | |||
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7â20
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Document Revision History
Table 7â6. Document Revision History (Part 2 of 2)
Date
May 2008
July 2007
March 2007
Version
Changes
Changes include addition of BLVD information
â Updated âIntroductionâ section with BLVDS information.
â Updated Figure 7â1 with BLVDS information and added Note 5.
â Updated Table 7â1 and added BLVDS information.
â Updated âCyclone III High-Speed I/O Banksâ section with BLVDS information.
â Updated Table 7â2 and 7â6.
â Added new section âBLVDS I/O Standard Support in Cyclone III Devicesâ.
1.2 â Updated Note 4 to Figure 7â4.
â Updated Note 1 to Figure 7â10.
â Updated Note 1 to Figure 7â11.
â Updated Note 1 to Figure 7â14.
â Updated âMini-LVDS I/O Standard Support in Cyclone III Devicesâ section.
â Updated Note 1 to Figure 7â17.
â Updated âLVPECL I/O Support in Cyclone III Devicesâ section.
â Added new Figure 7â18.
â Added note that PLL output clock pins do not support Class II type of selected differential
I/O standards.
â Added Table 8â3 that lists the number of differential channels which are migratable
across densities and packages.
â Updated (Note 4) to Figure 7â1.
1.1 â Updated (Note 3) to Table 7â1.
â Added new Table 7â3.
â Added (Note 1) to Figure 7â21.
â Added (Note 1) to Figure 7â23.
â Added chapter TOC and âReferenced Documentsâ section.
1.0 Initial release.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
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