|
EP3C5E144C8N Datasheet, PDF (300/348 Pages) Altera Corporation – Ability to disable external JTAG port | |||
|
◁ |
1â20
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1â28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
Unit
Min Typ Max Min Typ Max Min Typ Max
Output jitter
(peak to
â
peak)
â
â 500 â â 500 â
â 550
ps
20 â 80%,
tRISE
CLOAD = 5 pF
â 500 â
â 500 â
â 500 â
ps
tFALL
tLOCK (3)
20 â 80%,
CLOAD = 5 pF
â
â 500 â
â 500 â
â 500 â
ps
â â1
ââ1
â
â
1
ms
Notes to Table 1â28:
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported
at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation
|
▷ |