EP3C5E144C8N Datasheet, PDF (341/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 2: Cyclone III LS Device Data Sheet
Glossary
2–27
Table 2–39. Glossary (Part 2 of 6)
Letter
Term
D
—
E
—
F
f_HSCLK
GCLK
G
GCLK PLL
H HSIODR
Definitions
—
—
High-speed I/O Block: High-speed receiver and transmitter input and output clock frequency.
Input pin directly to the global clock network.
Input pin to the global clock network through the PLL.
High-speed I/O Block: Maximum and minimum LVDS data transfer rate (HSIODR = 1/TUI).
Input Waveforms
I
for the SSTL
Differential I/O
VSWING
Standard
V_IH
V_REF
V_IL
TMS
TDI
TCK
J JTAG Waveform
TDO
Signal
to be
Captured
Signal
to be
Driven
K
—
L
—
M
—
N
—
O
—
t _JCP
t _JCH
t _JCL
t _{JPSU_TDI}
t _{JPSU_TMS}
t_JPZX
t_JSSU
t_JPCO
t _JSH
t_JSZX
t_JSCO
—
—
—
—
—
t _JPH
t _JPXZ
t_JSXZ
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 2