EP3C5E144C8N Datasheet, PDF (117/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 6: I/O Features in the Cyclone III Device Family
I/O Banks
6–19
Table 6–6. Number of VREF Pins Per I/O Banks for Cyclone III and Cyclone III LS Devices (Part 2 of 2)
Family
Device
I/O Banks
Package Pin Count
1
2
3
4
5
6
7
8
EP3CLS70
EP3CLS100
EP3CLS150
EP3CLS200
UBGA
FBGA
FBGA
UBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
278
3
3
3
3
3
3
3
3
278
3
3
3
3
3
3
3
3
413
3
3
3
3
3
3
3
3
278
3
3
3
3
3
3
3
3
278
3
3
3
3
3
3
3
3
413
3
3
3
3
3
3
3
3
210
3
3
3
3
3
3
3
3
413
3
3
3
3
3
3
3
3
210
3
3
3
3
3
3
3
3
413
3
3
3
3
3
3
3
3
Each I/O bank of the Cyclone III device family has its own VCCIO pins. Each I/O bank
can support only one V_CCIO setting from among 1.2, 1.5, 1.8, 3.0, or 3.3 V. Any number
of supported single-ended or differential standards can be simultaneously supported
in a single I/O bank, as long as they use the same V_CCIO levels for input and output
pins.
When designing LVTTL/LVCMOS inputs with Cyclone III and Cyclone III LS
devices, refer to the following guidelines:
■ All pins accept input voltage (V_I) up to a maximum limit (3.6 V), as stated in the
recommended operating conditions are provided in the Cyclone III Device Data
Sheet and Cyclone III LS Device Data Sheet chapters.
■ Whenever the input level is higher than the bank V_CCIO, expect higher leakage
current.
■ The LVTTL/LVCMOS I/O standard input pins can only meet the V_IH and V_IL
levels according to bank voltage level.
Voltage-referenced standards are supported in an I/O bank using any number of
single-ended or differential standards, as long as they use the same V_REF and V_CCIO
values. For example, if you choose to implement both SSTL-2 and SSTL-18 in your
Cyclone III and Cyclone III LS devices, I/O pins using these standards—because they
require different V_REF values—must be in different banks from each other. However,
the same I/O bank can support SSTL-2 and 2.5-V LVCMOS with the V_CCIO set to
2.5 V and the V_REF set to 1.25 V.
1 When using Cyclone III and Cyclone III LS devices as a receiver in 3.3-, 3.0-, or 2.5-V
LVTTL/LVCMOS systems, you are responsible for managing overshoot or
undershoot to stay in the absolute maximum ratings and the recommended operating
conditions, provided in the Cyclone III Device Data Sheet and Cyclone III LS Device Data
Sheet chapters.
1 The PCI clamping diode is enabled by default in the Quartus II software for input
signals with bank V_CCIO at 2.5, 3.0, or 3.3 V.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1