EP3C5E144C8N Datasheet, PDF (83/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Phase Shift Implementation
5–23
Fine resolution phase shifts are implemented by allowing any of the output counters
(C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution. Equation 5–1
shows the minimum delay time that you can insert using this method.
Equation 5–1. Fine Resolution Phase Shift
Φ_fine
=
T_{----V----C---O--}
8
=
-------¹-------
8f_VCO
=
--------^N-----------
8Mf_REF
Note to Equation 5–1:
(1) f_REF is the input reference clock frequency
For example, if f_REF is 100 MHz, N = 1, and M = 8, then f_VCO = 800 MHz, and
Φfine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that
depends on reference clock frequency and counter settings.
Coarse resolution phase shifts are implemented by delaying the start of the counters
for a predetermined number of counter clocks. Equation 5–2 shows the coarse phase
shift.
Equation 5–2. Coarse Resolution Phase Shift
Φ_coarse
=
C_------–_-----1_-
f_VCO
=
-⁽--^C-----^–-----¹---⁾---^N---
Mf_REF
Note to Equation 5–2:
(1) C is the count value set for the counter delay time—the initial setting in the PLL usage section of the compilation
report in the Quartus II software. If the initial value is 1, C – 1 = 0° phase shift.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1