AK4679EG Datasheet, PDF (99/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
3. Dynamic Range Control Block
The AK4679 has the dynamic range control (DRC) circuits. The compression level is selected in three levels and set by
DRCC1-0 bits (Table 65).
When the DRC is OFF (DRCC1-0 bits = “00”), the audio data passes this block by 0dB gain. However limiter and
recovery operation is always ON. The compression level must be set when PMDRC bit = “0”.
Low Mid
DRC Off
0dB
High
-6dB
-6dB
0dB
DRC Input Level (dB)
Figure 75. DRC Gain Curve
+3.5dB
DRCC1 bit DRCC0 bit Compression Level
0
0
OFF
0
1
Low
1
0
Middle
1
1
High
Table 65. DRC Compression Level Setting
(default)
1. DRC Limiter Operation
During the DRC limiter operation, when the output level of DRC exceeds full-scale, the DRC volume are attenuated
automatically with the soft transition in the attenuation speed set by DLMAT2-0 bits (Table 66).
DLMAT2
bit
0
0
0
0
1
1
1
1
DLMAT1 DLMAT0
ATT Speed
bit
bit
8kHz
16kHz
44.1kHz
0
0
0.1dB/ms 0.3dB/ms 0.7dB/ms
0
1
0.3dB/ms 0.5dB/ms 1.5dB/ms
1
0
0.5dB/ms 1.1dB/ms 3.0dB/ms
1
1
1.1dB/ms 2.2dB/ms 6.0dB/ms
0
0
2.2dB/ms 4.4dB/ms 12.2dB/ms
0
1
4.5dB/ms 9.0dB/ms 24.7dB/ms
1
0
N/A
1
1
Table 66. DRC ATT Speed Setting (N/A: Not available)
(default)
MS1402-E-06
- 99 -
2013/02