AK4679EG Datasheet, PDF (10/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
PIN/FUNCTION (Cont.)
No. Pin Name I/O Function
Analog Output
B6 ^ROUT
LON
O Rch Stereo Line Output Pin (LODIF bit = “0”: Stereo Line Output)
O Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
B7 ^LOUT
LOP
O Lch Stereo Line Output Pin (LODIF bit = “0”: Stereo Line Output)
O Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
A4 RCP
O Receiver-Amp Positive Output Pin
B4 RCN
O Receiver-Amp Negative Output Pin
E8 HPL
O Lch Headphone-Amp Output Pin
E9 HPR
O Rch Headphone-Amp Output Pin
B1 SPP
O Speaker-Amp Positive Output Pin
A2 SPN
O Speaker-Amp Negative Output Pin
C1 SPFIL
O
Speaker-Amp Filter Pin
Connect 2.2nF between SPFIL pin and VSS1.
Control Interface for Audio Block
G6 SCLA
I Control Data Clock Pin
H7 SDAA
I/O Control Data Input Pin
G7 PDNA
I
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
Note 1. All input pins except analog input pins (LIN1/IN1+, RIN1/IN1−, LIN2/IN2-, RIN2/IN2+, LIN3/IN3+,
RIN3/IN3−, LIN4, RIN4) must not be allowed to float.
I/O pins (LRCK, BICK and SDAA pins) should be processed appropriately.
NO Pin Name
DSP I/O
G1 VDDE
D1 TVDDE
F1 VSS4
D7 PDNE
G3 ^STO
RDY
G5 SYNC1
F6 BCLK1
F5 SDIN1
H1 SDOUT1
D6 SYNC2
F2 BCLK2
D3 SDIN2
C4 SDOUT2
D5 ^SYNC3
JX1
F3 ^BCLK3
JX0
E3 SDIN3
F4
SDOUT3
GP0
C3 SDIN4
I/O
Function
- Core Power Supply Pin 1.2V
- I/O power Supply Pin 1.6∼3.6V
- Ground pin 0V
Power-Down Mode Pin
I “H”: Power-up, “L”: Power-down, reset the control register.
The AK4679 DSP must be reset once upon power-up.
Status Output Pin
O
Data Write Ready output pin for control I/F
(STRDY bit = “0”)
(STRDY bit = “1”)
I ^{Frame Sync 1 pin}
I
Serial Data Clock 1 Pin
AK4679 DSP goes into stanby state when BCLK1 is not present.
I Serial Data Input 1 Pin
O ^{Serial Data Output 1 Pin}
O Frame Sync 1 pin
O Serial Data Clock 2 Pin
I Serial Data Input 2 Pin
O Serial Data Output 2 Pin
I ^{Frame Sync 3 pin}
Conditional Jump 1 Pin
(SELPT bit = “1”)
(SELPT bit = “0”)
I ^{Serial Data Clock 3 Pin}
Conditional Jump 0 Pin
I Serial Data Input 3 Pin
(SELPT bit = “1”)
(SELPT bit = “0”)
O
Serial Data Output 3 Pin
DSP Programmable output 0 Pin
(SELDO3 bit = “0”)
(SELDO3 bit = “1”)
I Serial Data Input 4 Pin
MS1402-E-06
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2013/02