AK4679EG Datasheet, PDF (112/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = “1”, LOUT/ROUT pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins in full-differential as (L+R) signal.
The load impedance is 10kΩ (min) for each LOP pin and LON pin. When the PMLO = PMRO bits = “0”, the mono line
output enters power-down mode and the output is pulled-down to VSS1. When the PMLO = PMRO bits = “1” and LOPS
bit = “1”, mono line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO and
PMRO bits when LOPS bit = “1”. When PMLO = PMRO bits = “1” and LOPS bit = “0”, mono line output enters in
normal operation. LVL2-0 bits set the volume of mono line output.
DAC Lch
DACL bit
LVL2-0 bits
LOP pin
DAC Rch
M
I
X
DACR bit
LON pin
Figure 80. Full-differential Mono Line Output
LVL2-0 bits
Attenuation
7H
N/A
6H
N/A
5H
+12dB
4H
+9dB
3H
+6dB
(default)
2H
+3dB
1H
0dB
0H
−3dB
Table 102. Mono Line Output Gain Setting (N/A: Not available)
LOPS bit
0
1
PMLO/RO bits
Mode
LON/LOP pins
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to common voltage
Table 103. Mono Line Output Mode Setting
(default)
MS1402-E-06
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2013/02