AK4679EG Datasheet, PDF (180/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
Addr
80H
Register Name
DVLC Filter Select
R/W
Default
D7
DLLPF1
R/W
0
D6
DLLPF0
R/W
0
D5
DMHPF1
R/W
0
D4
DMHPF0
R/W
0
D3
DMLPF1
R/W
0
D2
DMLPF0
R/W
0
D1
D0
DHHPF1 DHHPF0
R/W R/W
0
0
DHHPF1-0: DVLC High Frequency Range HPF Coefficient Setting Enable (Table 58)
00: Disable (default)
01: 1st order HPF
10: 2nd order HPF
11: N/A
When DHHPF1-0 bits are “01” or “10”, the settings of DHHA13-0 and DHHB13-0 bits are enabled. When
DHHPF1-0 bits are “00”, HPF block outputs “0” data.
DMLPF1-0: DVLC Middle Frequency Range LPF Coefficient Setting Enable (Table 54)
00: Disable (default)
01: 1st order LPF
10: 2nd order LPF
11: N/A
When DMLPF1-0 bits are “01” or “10”, the settings of DMLA13-0 and DMLB13-0 bits are enabled. When
DMLPF1-0 bits are “00”, LPF block of DVLC middle frequency range is through (0dB).
DMHPF1-0: DVLC Middle Frequency Range HPF Coefficient Setting Enable (Table 53)
00: Disable (default)
01: 1st order HPF
10: 2nd order HPF
11: N/A
When DMHPF1-0 bits are “01” or “10”, the settings of DMHA13-0 and DMHB13-0 bits are enabled. When
DMHPF1-0 bits are “00”, HPF block of DVLC middle frequency range is through (0dB).
DLLPF1-0: DVLC Low Frequency Range LPF Coefficient Setting Enable (Table 49)
00: Disable (default)
01: 1st order LPF
10: 2nd order LPF
11: N/A
When DLLPF1-0 bits are “01” or “10”, the settings of DLLA13-0 and DLLB13-0 bits are enabled. When
DLLPF1-0 bits are “00”, LPF block outputs “0” data.
Addr
81H
Register Name
DVLC Mode Control
R/W
Default
D7
DVRGAIN2
R/W
0
D6
DVRGAIN1
R/W
1
D5
DVRGAIN0
R/W
1
D4
D3
D2
DVLMAT2 DVLMAT1 DVLMAT0
R/W
R/W
R/W
0
1
1
D1
DAF1
R/W
1
D0
DAF0
R/W
1
DAF1-0: Moving Average Parameter Setting for DVLC (Table 62)
Default: “11” (Default: 2048/fs)
DVLMAT2-0: DVLC ATT Speed Setting (Table 63)
Default: “011”
DVRGAIN2-0: DVLC Recovery Speed Setting (Table 64)
Default: “011”
MS1402-E-06
- 180 -
2013/02