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AK4679EG Datasheet, PDF (197/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP | |||
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[AK4679]
7. Timing
7-1. RAM Writing Timing during DSP Reset
Write to Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during DSP reset in the order
of command code, address and data. The PRAM start address is fixed to 0h. When writing the data to consecutive
address locations, continue to input data only. PRAM address is incremented by 1 automatically.
DSPRSTN bit = â0â
CSN
DLRDY bit = â1â
SCLK
SI
donât care
(L/H)
Command
Address
DATA DATA
DATA
DATA
DATA
donât care
(L/H)
RDY = âHâ
Address[n]
Address[n+1]
Figure 138. Writing to RAM at Consecutive Address Locations
When writing data at specified address locations, set the CSN pin to âLâ from âHâ and then input command code, address
and data in this order.
DSPRSTN bit = â0â
CSN
DLRDY bit
SCLK
donâtcare
SI (L/H)
RDY = âHâ
Command Address DATA
donâtcare
(L/H)
Command Address DATA
donâtcare
(L/H)
Figure 139. Writing to RAM at specified Address Locations
MS1402-E-06
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2013/02
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