AK4679EG Datasheet, PDF (31/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

■ Timing Diagram
MCKI
1/fCLK
tCLKH
tCLKL
1/fs
VIH1
VIL1
LRCK
tLRCKH
tLRCKL
tBCK
50%TVDDA
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
BICK
50%TVDDA
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
Figure 5. Clock Timing (PLL/EXT Master mode)
[AK4679]
LRCK
tLRCKH
tDBF
50%TVDDA
BICK
(BCKP = "0")
50%TVDDA
BICK
(BCKP = "1")
SDTO
SDTI
tBSD
tSDS
MSB
tSDH
50%TVDDA
50%TVDDA
VIH1
VIL1
Figure 6. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit= “0”)
MS1402-E-06
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2013/02