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AK4679EG Datasheet, PDF (15/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP
◁
[AK4679]
Parameter
min
typ
max
Unit
Stereo DAC Characteristics:
Resolution
-
-
24
Bits
Stereo Line Output Characteristics: Stereo DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, OVOL=0dB,
LVL=0dB, RL=10kΩ; unless otherwise specified.
Output Voltage (Note 17)
1.62
1.8
1.98
Vpp
S/(N+D) (0dBFS)
70
80
-
dB
S/N (A-weighted)
82
92
-
dB
Interchannel Isolation
85
95
-
dB
Interchannel Gain Mismatch
-
0
0.8
dB
Load Resistance
10
-
-
kΩ
Load Capacitance
-
-
30
pF
PSRR (Note 18)
217Hz
-
75
-
dB
1kHz
-
75
-
dB
Mono Line Output Characteristics: Stereo DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, OVOL=0dB, LVL=0dB,
LODIF bit = “1”, RL=10kΩ for each pin (Full-differential)
Output Voltage (Note 19)
3.24
3.6
3.96
Vpp
S/(N+D) (0dBFS)
-
73
-
dB
S/N (A-weighted)
-
95
-
dB
Load Resistance (LOP/LON pins, respectively)
(Note 20)
10
-
-
kΩ
Load Capacitance (LOP/LON pins, respectively)
(Note 21)
-
-
30
pF
PSRR (Note 18)
217Hz
-
70
-
dB
1kHz
-
70
-
dB
Mono Receiver-Amp Output Characteristics:
DAC(Stereo, Note 22) → RCP/RCN pins, ALC=OFF, IVOL=0dB, OVOL=0dB, RCVG=−6dB, RL=32Ω, BTL; unless
otherwise specified.
Output Voltage (Note 23)
0dBFS
1.76
1.96
2.16
Vpp
0dBFS, RCVG=0dB
-
3.91
-
Vpp
S/(N+D)
0dBFS
40
59
-
dB
0dBFS, RCVG=0dB
S/N (A-weighted) (DAC Æ RCP/RCN pins)
-
55
84
94
-
dB
-
dB
Output Noise Level (A-weighted, RCVG = −9dB)
-
−100
-
dBV
Load Resistance
32
-
-
Ω
Load Capacitance (Note 21)
-
-
30
pF
PSRR (Note 18)
217Hz
-
75
-
dB
1kHz
-
75
-
dB
Note 17. Output voltage is proportional to AVDD voltage. Vout = 1.0 x AVDD Vpp(typ)
Note 18. PSRR is referred to SVDD with 200mVpp sine wave.
Note 19. Output voltage is proportional to AVDD voltage. Vout = (LOP) – (LON) = 2.0 x AVDD Vpp(typ)
Note 20. This is a resistance value between output pin and VSS1. When a resistor is connected between output pins, load
resistance for each output pin is half. Therefore, it is necessary to decide load resistance in consideration of
these.
Note 21. This is a capacitance value between output pin and VSS1. When a capacitor is connected between output pins,
load capacitance for each output pin doubles. Therefore, it is necessary to decide load capacitance in
consideration of these.
Note 22. Input signal of left and right channels is same phase and level.
Note 23. Output voltage is proportional to AVDD voltage. Vout = (RCP) – (RCN) = 2.17 x AVDD Vpp(typ)
Po = 15mW @ 32Ω, Vout = 1.96Vpp. Po = 60mW @ 32Ω, Vout = 3.91Vpp.
MS1402-E-06
- 15 -
2013/02
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