AK4679EG Datasheet, PDF (48/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ PLL Mode (PMPLL bit = “1”) (Audio I/F)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates clock that is selected by the PLL3-0
and FS3-0 bits. The PLL lock time is shown in Table 5. This lock time is when the audio I/F is supplied stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency changes.
1) Setting of PLL Mode
PLL3 PLL2 PLL1 PLL0 PLL Reference
Input
PLL Lock
Mode
bit
bit
bit
bit Clock Input Pin Frequency
Time
(max)
2
0
0
1
0
BICK pin
32fs
2ms
3
0
0
1
1
BICK pin
64fs
2ms
4
0
1
0
0
MCKI pin 11.2896MHz 10ms
5
0
1
0
1
MCKI pin
12.288MHz 10ms
6
0
1
1
0
MCKI pin
12MHz
10ms
7
0
1
1
1
MCKI pin
24MHz
10ms
8
1
0
0
0
MCKI pin
19.2MHz
10ms
10
1
0
1
0
MCKI pin
13MHz
10ms
11
1
0
1
1
MCKI pin
26MHz
10ms
12
1
1
0
0
MCKI pin
13.5MHz
10ms
13
1
1
0
1
MCKI pin
27MHz
10ms
14
1
1
1
0
MCKI pin
25MHz
10ms
Others
Others
N/A
Table 5. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
(default)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI and BICK pins, the sampling frequency is selected by FS3-0 bits as defined in
Table 6.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency (Note
74)
0
0
0
0
0
8kHz mode
1
0
0
0
1
12kHz mode
2
0
0
1
0
16kHz mode
3
0
0
1
1
24kHz mode
5
0
1
0
1
11.025kHz mode
7
0
1
1
1
22.05kHz mode
10
1
0
1
0
32kHz mode
11
1
0
1
1
48kHz mode
15
1
1
1
1
44.1kHz mode
(default)
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (N/A: Not available)
Note 74. When the MCKI pin is the PLL reference clock input, the sampling frequency generated by PLL differs from the
sampling frequency of mode name in some combinations of MCKI frequency(PLL3-0 bits) and sampling
frequency (FS3-0 bits). Refer to Table 7 for the details of sampling frequency. In master mode, LRCK and BICK
output frequency correspond to sampling frequencies shown in Table 7. When the BICK pin is the PLL reference
clock input, the sampling frequency generated by PLL is the same sampling frequency of mode name.
MS1402-E-06
- 48 -
2013/02