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AK4679EG Datasheet, PDF (158/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP | |||
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[AK4679]
â Register Definition
Addr
00H
Register Name
Power Management 0
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
PMADR PMADL
0
0
PMPFIL PMVCM
R
R
R/W
R/W
R
R
R/W
R/W
0
0
0
0
0
0
0
0
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to â1â. PMVCM bit can be set to â0â only
when all power management bits are â0â.
PMPFIL: Programmable Filter Block Power Management
0: Power down (default)
1: Power up
PMADL: MIC-Amp Lch & ADC Lch Power Management
0: Power down (default)
1: Power up
When the PMADL(PMDML) or PMADR(PMDMR) bit is changed from â0â to â1â, the digital initialization
cycle (1059/fs=24ms @ 44.1kHz, ADRST bit = â0â) starts. After initializing, digital data of the ADC is
output.
PMADR: MIC-Amp Rch & ADC Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing â0â in each bit of this address. When the PDNA pin is âLâ,
Audio blocks are powered-down regardless of setting of this address. In this case, CODEC register is initialized to the
default value.
When all power management bits are â0â, Audio blocks are powered-down. The register values remain unchanged.
Power supply current is 50μA(typ) in this case. For fully shut down (typ. 1μA), PDNA pin should be âLâ.
MS1402-E-06
- 158 -
2013/02
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