AK4679EG Datasheet, PDF (47/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ CODEC System Clock (Audio I/F)
There are the following four clock modes to interface with external devices. (Table 2 and Table 3)
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: BICK pin)
EXT Slave Mode
EXT Master Mode
PMPLL bit
1
M/S bit
1
1
0
0
0
0
1
Table 2. Clock Mode Setting (x: Don’t care)
PLL3-0 bits
Table 5
Table 5
x
x
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: BICK pin)
EXT Slave Mode
EXT Master Mode
MCKI pin
BICK pin
Selected by PLL3-0
Output
bits
(Selected by BCKO bit)
GND
Input
(Selected by PLL3-0 bits)
Selected by FS1-0 bits
Input
(≥ 32fs)
Selected by FS1-0 bits
Output
(Selected by BCKO bit)
Table 3. Clock pins state in Clock Mode
Figure
Figure 39
Figure 40
Figure 41
Figure 42
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
■ Master Mode/Slave Mode (Audio I/F)
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. The audio
I/F is in slave mode until the M/S bit is changed to “1” after the PDNA pin changes from “L” to “H”. The AK4679 goes
to master mode by changing M/S bit = “1”.
When the audio I/F is used in master mode, LRCK and BICK pins are Hi-Z state until M/S bit becomes “1”. LRCK and
BICK pins of the audio I/F should be pulled-down or pulled-up by a resistor (about 100kΩ) externally to avoid floating
state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 4. Select Master/Slave Mode
(default)
MS1402-E-06
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2013/02