AK4679EG Datasheet, PDF (134/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ DSP Block Sampling Frequency Setting
Select sampling frequency (FSD[3:0] bits) on the sleep mode. In FSD mode 6, the Up-Down sampling converter is
powered-up and the AK4679 enters double sampling mode (fs1 =8kHz, fs2 =16kHz). In the other modes (using unity
sampling rate), fs2 is output at the same timing of fs1 input.
FSD
Mode
0
6
1
2
3
5
7
10
11
15
Others
FSD3 bit
0
0
0
0
0
0
0
1
1
1
FSD2 bit FSD1 bit FSD0 bit
Sampling Frequency
fs1 Port1 fs2 Port2 fs3 Port3
0
0
0
8kHz
8kHz
8kHz
1
1
0
8kHz
16kHz
8kHz
0
0
1
12kHz
12kHz
12kHz
0
1
0
16kHz
16kHz
16kHz
0
1
1
24kHz
24kHz
24kHz
1
0
1
11.025kHz 11.025kHz 11.025kHz
1
1
1
22.05kHz 22.05kHz 22.05kHz
0
1
0
32kHz
32kHz
32kHz
0
1
1
48kHz
48kHz
48kHz
1
1
1
44.1kHz
44.1kHz 44.1kHz
N/A
N/A
Table 123. Setting of Sampling Frequency (N/A: Not available)
(default)
Double FS mode
■ Selection of Input Port
The selection of the signal path of the input clock for Port#1 and #3 is set by the SELPT bit. SYNC2 clock is selected by
FSD bits and processed on the clock generator (CGU) block. The frequency of SYNC2 is double as that of SYNC1 on the
FSD mode 6 while the BCLK2 bit clock rate is same as BCLK1. When PT2N bit = “1”, BCLK2 and SYNC2 pin outputs
are low level. When BCLK1 and SYNC1 pins are selected as input pins, BCLK3/JX0 and SYNC3/JX1 pins could act as
JX0 and JX1 pins function respectively.
Port#1,#3
Port#2
BCLK1 pin
BCLK3/JX0 pin
SYNC1 pin
SYNC3/JX1 pin
SELPT bit _{FSD[3:0] bit} ^{PT2N bit}
CGU
BCLK2 pin
SYNC2 pin
CGU: Clock Generator Unit
Figure 108. Port#1/2/3 Signal Setting (PT2N bit = “0”)
MS1402-E-06
- 134 -
2013/02