AK4679EG Datasheet, PDF (77/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0, LFST and FR bits
Manual Mode
WR (IVL7-0)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Zero Crossing Timeout Period = 32ms@8kHz
Limiter and Recovery Step = 1
Fast Recovery = Enable (4 step)
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
(1) Addr=11H, Data=E1H
WR (IVR7-0)
(2) Addr=12H, Data=E1H
WR (REF7-0) ^{* The value of IVOL should be}
the same or smaller than REF’s
WR (ZTM1-0, WTM2-0, RFST1-0, FR)
(3) Addr=13H, Data=E1H
(4) Addr=15H, Data=05H
WR (LMTH1-0, RGAIN1-0, LMAT1-0, ZELMN, LFST)
(5) Addr=16H, Data=01H
WR (ALC = “1”)
(6) Addr=17H, Data=03H
ALC Operation
Note : WR : Write
Figure 67. Registers set-up sequence at ALC operation
MS1402-E-06
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2013/02