AK4679EG Datasheet, PDF (152/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ SPI Serial Control Interface (DSP block)
DSP block can be controlled by SPI.
1. Configuration
The access format is: Command code (8bit) + Address + Data (MSB First)
Bit Length
Rgister address 8
MSB bit is R/W flag. The following 7bits indicate access area such as PRAM/
or
CRAM/Registers.
Command code
Address to be 16 or 0
Valid only for those cases where accessed areas have addresses such as PRAM
accessed
/CRAM/OFREG. When no address is assigned, there is no data.
Data
later section Write or Read data
Note 79. SOPCFG bit selects SO output (Hi-z or Low) during CSN = “H”.
CSN
SCLK
SI
don’ tc a re
(L /H)
Re gAd dr,Co mCo de(8b it)
Address (16bit or 0bit)
Data (write)
SO ^Hi-Z
Low
Data (read)
The output level of SO pin is set by SOCFG bit on CSN pin = “H”.
□ Echo back
The input data of the SI pin is echoed back to the SO pin by shifting 8bit to the right.
1-1. Write Sequence 1
X (L/H)
H i-Z
Low
CSN
SI
COMMAND ADDRESS1 ADDRESS2
DATA1
DATA2
don’tcare
(L/H)
COMMAND
SO HiZ
Low
COMMAND ADDRESS1 ADDRESS2
DATA1
Hi-Z or Low
Figure 135. Echo-Back Writing 1
1-2 Write Sequence 2
ADDRESS1
COMMAND
CSN
SI
0xB4
0x00
0x00
DATA1
DATAn
Extra 8bit data
n= ~5
don’t care
(L/H)
SO ^HiZ
Low
COMMAND ADDRESS1 ADDRESS2
DATA1
DATAn
Hi-Z or Low
It is possible to verify the written data by inputting extra 8bit clock. If the dummy data is more than the data length, this
dummy data is written on the next address. (24bit for CRAM writing and 16bit for OFREG writing)
Figure 136. Echo-Back Writing 2
MS1402-E-06
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2013/02