AK4679EG Datasheet, PDF (136/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ PCM Audio Interface Format
LAW [1:0] and DIFD [1:0] bits select interface format of Port#1, Port#2 and Port#3. The interface format is in common
for all ports. BCLK1/2 frequency ranges from 16fsl to 256fsl. In all modes, the data format is MSB first, 2’s complement
and supporting 2channel data only. The data length supports 16/24bit Linear, 8bit μ-Law, and 8bit A-Law (Table 125).
On the PCM short/long frame, the AK4679 only accepts 1channel data when BICK1/2 is 16fs and in/output data length is
16bit Linear. The AK4679 can support 16bit PCM (short frame, long frame), Left justified and I²S mode (Table 126).
When the data format of Port#1 and Port#2 is 8bit A-Law or 8bitμ-Law, the data format of Port#3 will be 16bit Linear.
BCLK1 and BCLK3 input frequency to the Port#1, 3 are dependent on DIFD mode as shown below.
fBCLK1, fBCLK3 frequency range
Remark
4 x DataLength(8,16,24) x fs ~ 256 x fs
FSD mode 6
2 x DataLength (8,16,24) x fs ~ 256 x fs
Others
(Except FSD mode 6)
Table 124. BCLK Setting
Mode
0
1
2
3
LAW [1:0]bits
Digital I/F Format
Port#1, Port#2
Port#3
00
16-bit Linear
16-bit Linear
01
24-bit Linear
24-bit Linear
10
8-bit A-Law
16-bit Linear
11
8-bit μ-Law
16-bit Linear
Table 125. PCM Data Format Setting
(default)
DIFD Mode DIFD[1:0]bits
Digital I/F Format
BCLK1
0
00
PCM Short Frame
≥ 16fs1
1
01
PCM Long Frame
≥ 16fs1
2
10
Left justified
≥ 32fs1
3
11
I²S
≥ 32fs1
Table 126. PCM Interface Format Setting
In format mode 1/2, PCM data format is selected by BCKPD bi
(default)
When PCM short/long frame interface format is selected, the data format is determined by the BCKPD bit (Table 127).
SDOUT output data and SDIN input data are latched and output on the falling or rising edge of BCLK. Rising/Falling
edge select is valid on any digital interface format. Set BCKP1 bit = “0” (falling edge) for Left justified and I2S formats.
Refer to: Figure 110-Figure 113 for selectable format of BCLK against SYNC1/2 edge.
BCKPD bit
BCLK edge referenced
to SYNC edge
0
Falling (FE)
Figure 110 (default)
Figure 112
1
Rising (RE)
Figure 111
Figure 113
Table 127. PCM Interface format in (DIFD[1:0] = “00”, “01”)
MS1402-E-06
- 136 -
2013/02