AK4679EG Datasheet, PDF (208/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

4. EXT Master Mode
Power Supply
PDNA pin
PMVCM bit
(Addr:00H, D0)
MCKI pin
M/S bit
(Addr:04H, D1)
LRCK pin
BICK pin
(1)
(4)
(2)
(3)
[AK4679]
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(2) MCKI input
Input
(3)Addr:00H, Data:00H
Addr:03H, Data:F0H
Addr:04H, Data:02H
Addr:05H, Data02H
Output
BICK and LRCK output
(4) Addr:00H, Data:01H
Figure 152. Clock Set Up Sequence (4)
<Example>
(1) After Power Up, PDNA pin = “L” Æ “H”.
“L” time of 1.5μs or more is needed to reset the AK4679.
(2) MCKI should be input.
(3) Dummy command (Addr:00H, Data:00H) must be executed before control register is set.
After DIF1-0, CM1-0 and FS3-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output.
(4) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates. Power-up time of VCOM is maximum
1.5ms when the exterenal capacitor connected to the VCOM pin is 1μF.
MS1402-E-06
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2013/02