AK4679EG Datasheet, PDF (111/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
LOUT
ROUT
1μF
220Ω
2 0k Ω
Figure 78. External Circuit for Stereo Line Output (in case of using Pop Noise Reduction Circuit)
<Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)>
(2)
P M L O b it
P M R O b it
(1)
(3 )
LO PS bit
(5)
(4 )
(6)
L O U T p in
R O U T p in
≥ 300 m s
N o rm a l O utp u t
≥ 300 m s
Figure 79. Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(2) Set PMLO=PMRO bits = “1”. Stereo line output exits power-down mode.
LOUT and ROUT pins rise up to common voltage (typ. 0.8 x AVDD). Rise time is 200ms (max 300ms) at
C=1μF and AVDD=1.8V.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO=PMRO bits = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=1.8V.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits power-save mode.
MS1402-E-06
- 111 -
2013/02