AK4679EG Datasheet, PDF (56/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ Audio Interface Format
Four types of data formats are available and can be selected by setting the DIF1-0 bits (Table 18). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the audio I/F in master mode, but must be input to the audio I/F in slave mode.
Mode
0
1
2
DIF1
bit
0
0
1
3
1
DIF0
bit
0
1
0
1
SDTO (ADC)
SDTI (DAC)
16bit DSP Mode 16bit DSP Mode
24bit MSB justified 16bit LSB justified
24bit MSB justified
24/16 bit I²S
24bit MSB
justified
24/16bit I²S
compatible
compatible
Table 18. Audio Interface Format
BICK
≥ 32fs
≥ 32fs
≥ 48fs
32fs or
≥ 48fs
Figure
Table 19
Figure 50
Figure 51 (default)
Figure 52
If 24-bit(16-bit) data that ADC outputs is converted to 8-bit data by removing LSB 16-bit(8-bit), “−1” at 24bit(16bit) data
is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to
“−65536” at 24-bit (“−256” at 16-bit) data which is a large offset. This offset can be removed by adding the offset of
“32768” at 24-bit (“128” at 16bit) to 24-bit(16-bit) data before converting to 8-bit data.
In Mode 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge
(“↑”).
In Mode 0 (16bit DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 19).
DIF1
bit
0
DIF0
bit
0
MSBS
bit
0
0
1
1
BCKP
bit
Audio Interface Format
MSB of SDTO is output by the rising edge (“↑”) of the
0
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“↓”) of the
1
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“↑”) of the
falling edge (“↓”) of the first BICK after the rising edge
0 (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“↓”) of the
rising edge (“↑”) of the first BICK after the rising edge
1 (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
Table 19. Audio Interface Format in Mode 0
Figure
Figure 46
Figure 47
Figure 48
Figure 49
(default)
MS1402-E-06
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2013/02