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AK4679EG Datasheet, PDF (119/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP | |||
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[AK4679]
â Speaker Output (SPP/SPN pins)
Lch/Rch signal of DAC is converted by PWM and is output from SPP/SPN pins by BTL. When Lch/Rch signal of DAC
is 0dBFS, the speaker amplifier outputs 0.89W ( @ 8Ω, AVDD=1.8V, SVDD=4.2V, SPKG=-6dB). The load impedance
is 8Ω (min). A 2.2nF capacitor should be connected between SPFIL pin and VSS1 pin to reduce out-of-band noise from
DAC. SPKG3-0 bits control the volume of SPP/SPN.
SPKG3-0 bits
DACSL bit
DAC Lch
SPP pin
DAC Rch
M
I
X
DACSR bit
SPN pin
Figure 86. Mono Speaker Output
SPKG3-0 bits Attenuation
FH
+12dB
EH
+9dB
DH
+6dB
CH
+3dB
BH
0dB
(default)
AH
â3dB
9H
â6dB
8H
â9dB
7H
â12dB
6H
â15dB
5H
â18dB
4H
â21dB
3H
â24dB
2H
â27dB
1H
â30dB
0H
MUTE
Table 111. Speaker Output Volume Setting
PMSPK bit
Speaker-Amp
0
Power-down & Hi-Z
1
Power-up & Output
Table 112. Speaker-Amp output state
(default)
When PMSPK bit is â1â, the speaker-amp is powered-up. The power-up time of SPK-Amp block is 32ms and then SPP
and SPN pins output 0V (VSS3). When PMSPK bit is â0â, the SPK-Amp block can be powered-down. The clock
supplied to SPK-Amp block must not be stopped for more than 0.5ms. Once SPK-Amp block is powered-down, the
SPK-Amp block should be powered-up again with an interval of 0.5ms or more.
MS1402-E-06
- 119 -
2013/02
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