AK4679EG Datasheet, PDF (183/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ Register Map (DSP block)
The DSP block control register settings are executed through a microcontroller interface. All registers below are
initialized by the power down (PDNE pin = “L”). To ensure control register settings, this power-down (PDNE pin= “L”)
must always be made when power up the AK4679.
Control register settings should be made during DSP reset (DSPRSTN bit = “0”).
Name
D7
D6
D5
D4
D3
D2
PCONT0
0
0
0
SOCFG
0
0
PCONT1
0
0
0
0
0
0
D1
D0
0
PWSW
0
MRSTN
Name
CONT0
CONT1
CONT2
CONT3
CONT4
CONT5
D7
FSD[3]
LAW[1]
BANK[3]
POMOD
E
LPDO4
OUT4N
D6
FSD[2]
LAW[0]
BANK[2]
DRMS[1]
LPDO3
OUT3N
D5
D4
FSD[1] FSD[0]
DIFD[1]
BANK[1]
DRMS[0]
DIFD[0]
BANK[0
]
DRAD[1
]
LPDO2 LPDO1
OUT2N OUT1N
D3
0
BCKPD
LOCKE
DRAD[0]
SELDO4
0
CONT6
0
0
DLRDY
0
0
CONT7 SYDET CGLK
0
0
0
CONT8 TESTC
0
0
0
0
Note 83. The bits defined as 0 must set a “0” value.
Note 84. Default value is the value after power-down release.
D2
0
0
CRCE
0
SELDO3
0
DSPRST
N
0
0
D1
0
TESTB
D0
0
TESTA
WDTN
EFEN
WAVP1[1]
PT2N
0
WAVP1[0
]
SELPT
STRDY
0
0
0
0
0
0
MS1402-E-06
- 183 -
2013/02