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AK4679EG Datasheet, PDF (29/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP
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[AK4679]
Parameter
Symbol min
Control Interface Timing (I2C Bus mode): (Note 65, Note 66)
typ
max Unit
SCL Clock Frequency
fSCL
30
-
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
-
-
μs
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
-
-
μs
Clock Low Time
tLOW
1.3
-
-
μs
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 67)
tHIGH
0.6
-
tSU:STA 0.6
-
tHD:DAT
0
-
-
μs
-
μs
-
μs
SDA Setup Time from SCL Rising
tSU:DAT 0.1
-
-
μs
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3 μs
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3 μs
Setup Time for Stop Condition
tSU:STO 0.6
-
-
μs
Capacitive Load on Bus
Cb
-
-
400 pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
-
50
ns
Digital Audio Interface Timing: CL=100pF
DMCLK Output Timing
Period
tSCK
-
1/(64fs) -
ns
Rising Time
tSRise
-
-
10
ns
Falling Time
tSFall
-
-
10
ns
Duty Cycle
dSCK
45
50
55
%
Audio Interface Timing
DMDAT Setup Time
tDMS
50
-
-
ns
DMDAT Hold Time
tDMH
0
-
-
ns
Power-down & Reset Timing
PDNA Accept Pulse Width (Note 68)
tAPDA
1.5
-
-
μs
PDNE Accept Pulse Width (Note 68)
tAPDE
0.6
μs
PDN Reject Pulse Width (Note 68)
tRPD
-
-
50
ns
PMADL or PMADR “↑” to SDTO valid (Note 69)
ADRST bit = “0”
ADRST bit = “1”
tPDV
tPDV
-
1059
-
1/fs
-
267
-
1/fs
PMDML or PMDMR “↑” to SDTO valid (Note 70)
ADRST bit = “0”
tPDV
-
1059
-
1/fs
ADRST bit = “1”
tPDV
-
267
-
1/fs
PMSRAO “↑” to SDTOA valid (Note 71)
tPDV2
-
164
1/fs2
PMSRBO “↑” to SDTOB valid (Note 72)
tPDV3
-
164
1/fs3
Note 65. SDA means both SDAA and SDAE pins. SCL means both SCLA and SCLE pins.
Note 66. I2C-bus is a registered trademark of NXP B.V.
Note 67. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 68. The audio block of AK4679 can be reset by bringing PDNA pin = “L” to “H” only upon power up. The PDNA
pin must held “L” for more than 1.5μs for a certain reset. The DSP block can be reset by bringing PDNE pin =
“L” to “H” only upon power up. The PDNE pin must held “L” for more than 0.6μs for a certain reset. The
AK4679 is not reset by the “L” pulse less than 50ns.
Note 69. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
Note 70. This is the count of LRCK “↑” from the PMDML or PMDMR bit = “1”.
Note 71. This is the count of SYNCA “↑” from the PMSRAO bit = “1”.
Note 72. This is the count of SYNCB “↑” from the PMSRBO bit = “1”.
MS1402-E-06
- 29 -
2013/02
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