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AK4679EG Datasheet, PDF (210/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP | |||
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[AK4679]
â Headphone-Amp Output
FS3-0 bits
(Addr:03H, D7-4)
0000
(1)
1111
HPG5-0 bits
(Addr:0FH, D5-0)
5EQ bit
(Addr:17H, D3)
23H
0
(2)
(3)
20H
(8)
1
0
PMDAL/R bits
PMEQ bit
(Addr:01H, D3-2, D0)
PMHPL/R bits
(Addr:0BH, D1-0)
(4)
(5)
28ms
(7)
(6)
HPL/R pins
0V
Normal Output
0V
Example :
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
HP Volume Level: â6dB
5 band EQ: Enable
(1) Addr:03H, Data FxH
(2) Addr:0FH, Data 20H
(3) Addr:17H, Data 0AH
(4) Addr:01H, Data 0DH
(5) Addr:0BH, Data 03H
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(6) Addr:0BH, Data 00H
(7) Addr:01H, Data 00H
(8) Addr:17H, Data 02H
Figure 154. Headphone-Amp Output Sequence
(Headphone Playback: SDTI â Audio I/F â 5-band EQ â DATT-A â DACL/R â HPL/HPR)
<Example>
At first, clocks should be supplied according to âClock Set Upâ sequence.
19H
(1) Set up a sampling frequency (FS3-0 bits). DAC and Headphone-Amp should be powered-up in consideration
of VCOM rise time and PLL lock time after a sampling frequency is changed when the AK4679 is in PLL
mode.
(2) Set up analog volume for HP-Amp (Addr: 0FH, HPG5-0 bits)
(3) Enable 5-band Equalizer: 5EQ bit = â0â Ã â1â (Frequency Response and gain are selected by Addr =
50H-6EH.)
(4) Power up DAC and EQ : PMDAL = PMDAR = PMEQ bits = â0â â â1â
(5) Power up Headphone-Amp and charge pump circuit: PMHPL = PMHPR bits = â0â â â1â
The power-up time of HP-Amp block is 28ms. HPL and HPR pins output 0V until the power-up time of
HP-Amp block passes.
(6) Power down Headphone-Amp and charge pump circuit: PMHPL = PMHPR bits = â1â â â0â
HPL and HPR pins go to 0V.
(7) Power down DAC and EQ: PMDAL = PMDAR = PMEQ bits = â1â â â0â
(8) Disable 5-band Equalizer: 5EQ bit = â1â Ã â0â
MS1402-E-06
- 210 -
2013/02
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