AK4679EG Datasheet, PDF (23/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=PVDD=1.7 ~ 2.0V, VDDE=1.1~1.3V, TVDDA=TVDDE=1.6 ~3 .6V, SVDD=3.0 ∼ 5.5V;
C_L=20pF or 400pF (SDAA, SDAE pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
ns
Pulse Width High
tCLKH 0.4/fCLK
-
-
ns
LRCK Output Timing
Frequency
fs
-
Table 7
-
kHz
DSP Mode: Pulse Width High
tLRCKH
-
tBCK
-
ns
Except DSP Mode: Duty Cycle
Duty
-
50
-
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
-
1/(32fs)
-
ns
BCKO bit = “1”
tBCK
-
1/(64fs)
-
ns
Duty Cycle
dBCK
-
50
-
%
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
8
-
48
kHz
DSP Mode: Pulse Width High
tLRCKH tBCK−60
-
1/fs − tBCK ns
Except DSP Mode: Duty Cycle
Duty
45
-
55
%
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
-
1/(32fs)
-
ns
PLL3-0 bits = “0011”
tBCK
-
1/(64fs)
-
ns
Pulse Width Low
tBCKL 0.4 x tBCK
-
-
ns
Pulse Width High
tBCKH 0.4 x tBCK
-
-
ns
MS1402-E-06
- 23 -
2013/02