AK4679EG Datasheet, PDF (192/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ Write
Command Address
Code
0x80~0x8F 16bit
0x90~0x9F 16bit
0xA2
0xA4
0xB2
0xB4
0xB8
0xC0~0xC8
0xD0~0xD
1
0xF2
0xF4
16bit
16bit
16bit
16bit
16bit
None
None
None
None
Data Length Description
24bit×n
24bit×n
None
None
24bit×n
24bit×n
40bit×n
8bit
8bit
Write preparation to CRAM during RUN.
Command code BIT3~BIT0 bits determines the amount of write operation.
(0x80 # of write: 1, 0x81 # of write: 2, ----, 0x8F # of write: 16) If the actual
amount of write operations exceeds the defined amount, that data will be
ignored.
Write preparation to OFREG during RUN
Command code BIT3~BIT0 bits determines the amount of write operation.
(0x90 # of write: 1, 0x91 # of write: 2, ----, 0x9F # of write: 16) If the actual
amount of write operations exceeds the defined amount, that data will be
ignored.
Write operation to OFREG during RUN. 0 address should be written.
Write operation to CRAM during RUN. 0 address should be written.
Write operation to OFREG during DSP reset
Write operation to CRAM during DSP reset
Write operation to PRAM during DSP reset
Write operation to Register 0h~8h (except 7h)
System Power Supply Registers 0h~1h Write
16bit
8bit
CRC Write
Write operation of DSP JX code
Data length is defined by the command code which specifies the area to be accessed. When accessing RAM, data may be
read from sequential address locations by reading data continuously. Writing other than the above-mentioned command
code is prohibited.
■ Read
Table 132. List of Usable Command Codes in Write Sequence
Command Address Data
Description
Code
Length
0x24
16bit
24bit×n CRAM/OFREG Write preparation data Read during RUN
0x32
16bit
24bit×n Read operation form OFREG during DSP reset
0x34
16bit
24bit×n Read operation from CRAM during DSP reset
0x38
16bit
40bit×n Read operation from PRAM during DSP reset
0x40~0x48 None
8bit Read operation from Register 0h~8h
0x50~0x 51 None
8bit Read operation from System Power Supply Register 0h~1h
0x60
None
8bit Device Identification
0x70
None
8bit DSP Error Status Read
0x72
None
16bit CRC result Read
0x76
None
32bit Read operation from MIR1
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
0x78
None
32bit Read operation from MIR2
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
0x7A
None
32bit Read operation from MIR3
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
0x7C
None
32bit Read operation from MIR4
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
Reading other than the above-mentioned command code is prohibited.
Table 133. List of Usable Command Codes in Read Sequence
MS1402-E-06
- 192 -
2013/02