AK4679EG Datasheet, PDF (28/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
Parameter
Symbol
min
SYNC1/3, BCLK1/BCLK3 Input Timing
typ
max
Unit
SYNC1/3 Input Timing
SYNC1/3 frequency
fs
8
48
kHz
BCLK1 Input Timing (Note 60, Note 61) fBCLK
64
3072
kHz
Pulse width Low
tBCKL1 0.4 x tBCLK
ns
Pulse width High
tBCKH1 _{0.4x tBCLK}
ns
Note 60. SYNC1 and BCLK1 or SYNC3 and BCLK3 should be synchronized and their sampling rates (fs) should be
stable
Note 61. fBCLK ≥ 4 x N x fs (N=1, 2, 3….)
Parameter
Symbol
min typ max Unit
SDIN1, SDIN3, SDIN4, SDOUT1, SDOUT3, SDOUT4
Delay Time from BICLK1 “↑” to SYNC1 “↑”
(Note 62) tBSYD
20
ns
Delay Time from SYNC1 “↓” to BICK1 “↑”
(Note 62) tSYBD 100
ns
Serial Data Input Latch Setup Time
tB1IDS
40
ns
Serial Data Input Latch Hold Time
tB1IDH 40
ns
Delay Time from SYNC1 to Serial Data Output
tSY1OD
40
ns
Delay Time from BICK1 “↓” to Serial Data Output (Note 63) tB1OD
40
ns
SDIN2, SDOUT2
SYNC2 Duty cycle
50
%
Serial Data Input Latch Setup Time
tB2IDS
40
ns
Serial Data Input Latch Hold Time
tB2IDH 40
ns
Delay Time from SYNC2 to Serial Data Outputs
tSY2OD
40
ns
Delay Time from BCLK2 “↓”to Serial Data Output (Note 64) tB2OD
40
ns
SDINn → SDOUTn (n=1, 2, 3, 4)
Delay time from SDINn to SDOUTn Output
tIOD
60
ns
Note 62. BICK1 edge must not occur at the same time as SYNC1 edge.
Note 63. When the polarity of BICK1 is inverted, delay time is from BICK1 “↑”.
Note 64. When the polarity of BICK2 is inverted, delay time is from BICK2 “↑”
MS1402-E-06
- 28 -
2013/02