AK4679EG Datasheet, PDF (110/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ Stereo Line Output (LOUT/ROUT pins)
When DACL and DACR bits are “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins in single-ended.
When DACL and DACR bits are “0” in normal operation (PMDAC=PML/RO bits = “1”, LOPS bit = “0”), output signal
is muted and LOUT/ROUT pins output common voltage (typ. 0.8 x AVDD). The load impedance is 10kΩ (min.). When
the PMLO=PMRO=LOPS bits = “0”, LOUT/ROUT enters power-down mode and the output is pulled-down to VSS1 by
100kΩ (typ). When the LOPS bit is “1”, LOUT/ROUT enters power-save mode. Pop noise at power-up/down can be
reduced by changing PMLO and PMRO bits at LOPS bit = “1”. In this case, output signal line should be pulled-down to
VSS1 by 20kΩ after AC coupled as Figure 78. Rise/Fall time is 300ms (max) at C=1μF and AVDD=1.8V. When
PMLO=PMRO bits = “1” and LOPS bit = “0”, LOUT/ROUT is in normal operation. LVL2-0 bits control the volume of
LOUT/ROUT. When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R) mono signal.
DAC Lch
DACL bit
DACR bit x LOM bit
LVL2-0 bits
M
I
LOUT pin
X
DACL bit x LOM bit
DAC Rch
M
DACR bit
I
X
ROUT pin
Figure 77. Stereo Line Output
LOPS bit
0
1
PMLO bit
Mode
LOUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to common voltage
Table 99. Stereo Line Output Mode Select (LOUT)
(default)
LOPS bit
0
1
PMRO bit
Mode
ROUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to common voltage
Table 100. Stereo Line Output Mode Select (ROUT)
(default)
LVL2-0 bits
Attenuation
7H
N/A
6H
N/A
5H
+6dB
4H
+3dB
3H
0dB
(default)
2H
−3dB
1H
−6dB
0H
−9dB
Table 101. Stereo Line Output Volume Setting (N/A: Not available)
MS1402-E-06
- 110 -
2013/02