AK4679EG Datasheet, PDF (190/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
CONT6: Signal Setting 2
Register
Register Name
D7
Address
CONT6
0
WR
R/W
R
C6h 46h
Default
0
D6
D5
D4
0
DLRDY
0
R
R/W
R
0
0
0
D3
D2
D1
D0
0
DSPRSTN
0
0
R
R/W
R
R
0
0
0
0
DLRDY: DSP Download Preparation
0: download inhibit (default)
1: download ready
This bit is used when start to download the DSP programs. The bit must be cleared after downloading
programs are completed.
DSPRSTN: DSP Reset
0: DSP Reset (default)
1: DSP Reset Release
CONT7: State Signal (Read only)
Register
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Address
CONT7
SYDET CGLK
0
0
0
0
0
0
WR
R/W
R
R
R
R
R
R
R
R
C7h 47h
Default
0
0
0
0
0
0
0
0
DSP status output from the wait sync state to operational state (Run State)
SYDET: SYNC Signal Detection flag
0: No SYNC1 pin Signal (Low or High fixed) (default)
1: SYNC1 pin Signal Detect
This bit outputs DSP status in Wait Sync State until DSP Operational state (RUN).
CGLK: Clock Generator Unit Lock Status
0: Clock Generator Unlocked State (default)
1: Clock Generator Locked State
CONT8: Initial Setting 4
Register
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Address
CONT8
TESTC
0
0
0
0
0
0
0
WR
R/W
R/W
R
R
R
R
R
R
R
C8h 48h
Default
0
0
0
0
0
0
0
0
TESTC bit must be set “1”. (i.e. set the 80h value in this register)
The TESTC bit is set after writing the power control register with the power suplly on.
MS1402-E-06
- 190 -
2013/02