AK4679EG Datasheet, PDF (131/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
1/fs3
SYNCB
BICKB
(16 fs 3)
(16bit Linear)
SDTOB _{L1 L0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 LD10 L0 L15 L14 L13}
SDTIB
(8bit A-Law/μ-Law)
SDTOB _{R1 R0 L7 L6 L5 L4 L3 L2 L1 L0 R7 R6 R5 R4 R3 R2 RD10 R0 L7 L6 L5}
SDTIB
BICKB
(64 fs 3)
(16bit Linear)
SDTOB
L15 L14 L13 L8 L7 L1 L1 L0 R15 R13 R1 R0
L15 L14 L13
SDTIB Don’t Care _{L15 L14 L13 L8 L7 L1 L1 L0 R15 D6 R1 R0}
(8bit A-Law/μ-Law)
SDTOB
L7 L6 L6 L0 R7 R1 R1 R0
Don’t Care
L15 L14 L13
L7 L6 L5
SDTIB Don’t Care L7 L6 _{D5 L0 R7 D2 R1 R0}
D on’t Care
L7 L6 L5
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 102. Timing of Long Frame Sync (PCM I/F B MSBSB bit = “1”, BCKPB bit = “0”)
1/fs3
SYNCB
BICKB
(16 fs 3)
(16bit Linear)
SDTOB _{L1 L0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 LD10 L0 L15 L14 L13}
SDTIB
(8bit A-Law/μ-Law)
SDTOB _{R1 L0 L7 L6 L5 L4 L3 L2 L1 L0 R7 R6 R5 R4 R3 R2 RD10 R0 L7 L6 L5}
SDTIB
BICKB
(64 fs 3)
(16bit Linear)
SDTOB
L15 L14 L13 L8 L7 L1 L1 L0 R15 R13 R1 R0
L15 L14 L13
SDTIB Don’t Care _{L15 L14 L13 L8 L7 L1 L1 L0 R15 D6 R1 R0}
(8bit A-Law/μ-Law)
SDTOB
L7 L6 L6 L0 R7 R1 R1 R0
Don’t Care
L15 L14 L13
L7 L6 L5
SDTIB Don’t Care _{L7 L6 D5 L0 R7 D2 R1 R0}
D on’t Care
L7 L6 L5
<16bit Linear>
Lch Data: L15-0, MSB(L15), LSB(L0)
Rch Data: R15-0, MSB(R15), LSB(R0)
<8bit A-Law/μ-Law>
Lch D ata: L7-0, MSB(L7), LSB(L0)
Rch Data: R7-0, MSB(R7), LSB(R0)
Figure 103. Timing of Long Frame Sync (PCM I/F B: MSBSB bit = “1”, BCKPB bit = “1”)
MS1402-E-06
- 131 -
2013/02