AK4679EG Datasheet, PDF (54/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (Audio I/F)
The audio I/F becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs, or 1024fs). The
input frequency of MCKI is selected by CM1-0 bits (Table 13) and sampling frequency is selected by FS3-0 bits (Table
14).
Mode
0
1
2
3
CM1 bit CM0 bit MCKI Input Frequency Sampling Frequency Range
0
0
256fs
24kHz ∼ 48kHz
(default)
0
1
512fs
8kHz ∼ 24kHz
1
0
1024fs
8kHz ∼ 12kHz
1
1
256fs
8kHz ∼ 24kHz
Table 13. MCKI Frequency in EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
Mode
0
1
2
3
5
7
10
11
15
Others
FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency
0
0
0
0
8kHz
0
0
0
1
12kHz
0
0
1
0
16kHz
0
0
1
1
24kHz
0
1
0
1
11.025kHz
0
1
1
1
22.05kHz
1
0
1
0
32kHz
1
0
1
1
48kHz
1
1
1
1
44.1kHz
Others
N/A
Table 14. Setting of Sampling Frequency (N/A: Not available)
(default)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through
LOUT/ROUT pins at fs=8kHz is shown in Table 15.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
82dB
512fs
82dB
1024fs
92dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
CODEC
MCKI
B IC K
LRCK
256fs, 512fs, or
1024fs
32fs or 64fs
1f s
DSP
BCLKx
SYNCx
SDTO
SDTI
SDINx
SDOUTx
Figure 42. EXT Master Mode (x=1 to 4)
BCKO bit BICK Output Frequency
0
32fs
(default)
1
64fs
Table 16. BICK Output Frequency in Master Mode
MS1402-E-06
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2013/02