AK4679EG Datasheet, PDF (186/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
CONT2: Initial Setting 3
Register
Register Name
D7
D6
D5
D4
Address
CONT2
BANK[3:0]
WR
R/W
R/W
R/W
R/W
R/W
C2h 42h
Default
0
0
0
0
BANK[3:0]: DSP DLRAM Mode Setting
DLRAM
Partition
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BANK [3:0]
Bit
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Bank0
Ring 20.4f
16384 words
14336 words
12288 words
10240 words
8192 words
6144 words
4096 words
2048 words
0
10240 words
8192 words
6144 words
4096 words
2048 words
0
DSP Delay RAM
Bank1
Linear 20.4f
0
2048 words
4096 words
6144 words
8192 words
10240 words
12288 words
14336 words
16384 words
0
2048 words
4096 words
6144 words
8192 words
10240 words
N/A
LOCKE: Clock Generator Unit Lock Error status selects (Table 129)
0: lock status monitor invalid (default)
1: lock status monitor Enable
CRCE: DSP CRC status selects (Table 129)
0: CRC status monitor invalid (default)
1: CRC status monitor enable
WDTN: WDT Disable Switch of DSP (Table 129)
0: WDT Enable (default)
1: WDT Disable
EFEN: Extended Instruction Enable of DSP
0: Valid (default)
1: Invalid
D3
LOCKE
R/W
0
D2
CRCE
R/W
0
D1
WDTN
R/W
0
D0
EFEN
R/W
0
Bank2
Linear 8bit
μ-law codec
0
0
0
0
0
0
0
0
0
18432words
18432words
18432words
18432words
18432words
18432words
(default)
(N/A: Not available)
MS1402-E-06
- 186 -
2013/02