AK4679EG Datasheet, PDF (202/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
SYSTEM DESIGN
Figure 147 and Figure 148 show the system connection diagram for the AK4679. An evaluation board [AKD4679]
439H
40H
demonstrates the optimum layout, power supply arrangements and measurement results.
Digital
Ground
Analog
Ground
Top View
1.8V
2.2u
0.1u 2.2u
LIN2
RIN2
LIN1
LIN3
HPR
PVDD
CNA
VSS5
CNB
2.2u
Analog
1.7 ∼ 2.0V
1u
0.1u
VSS1 CSN_SCLE RIN1
RIN3
VCOM
LOUT SCLK_CAD0 PDNE
HPL
RIN4
VEE
VEE
CPA
CPB
LIN4
PDNA
SDAA
VSS2
AVDD
ROUT SI_CAD1 SYNC2
10u
BCLK1
SCLA
SDTO
TVDDA
AK4679
MPWR1 MPWR2 SO_SDAE JX1_SYNC3
SDIN1
SYNC1
LRCK
BICK
0.1u
Digital I/O
CODEC
1.6 ∼ 3.6V
RCP
RCN
SDOUT2
TEST SDOUT3_GP0 SYNCA SDTOB
SDTI
SVDD
VSS3
SDIN4
SDIN2
SDIN3 JX0_BCLK3 STO_RDY SYNCB
MCKI
Analog
3.0 ∼ 5.5V
10u
0.1u
SPN
VSS3
I2CE SDOUT4_GP1 SDTIA
BCLK2
BICKA
BICKB
SDTOA
SVDD
SPP
SPFIL
TVDDE
DVDD
VSS4
VDDE SDOUT1 SDTIB
0.1u
0.1u
0.1u
DSP Core
1.1 ∼ 1.3V
Digital I/O
DSP
1.6 ∼ 3.6V
Digital Core
1.7 ∼ 2.0V
Note:
- VSS1, VSS2, VSS3, VSS4 and VSS5 of the AK4679 should be distributed separately from the ground of
external controllers.
- 0.1μF capacitors at power supply pins should be ceramic capacitors. 2.2μF±50% capacitors between the CPA
to CNA pins, the CPB to CNB pins and the VEE to VSS5 pins should be low ESR ceramic capacitors. These
capacitors must be connected as close as possible to the pins.
Figure 147. Typical Connection Diagram (Power Supply Block)
MS1402-E-06
- 202 -
2013/02