AK4679EG Datasheet, PDF (90/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
Slope Setting
Y 1_L
L1G =
X1_L
x 16, L2G =
(Y2_L – Y1_L)
(X2_L – X1_L)
x 16,
L3G = ^{(Y3L – Y2L)} x 16, L4G = ^{(Y4L – Y3L)} x 16,
(X3_L – X2_L)
(X4_L – X3_L)
The results calculated by the equations above should be rounded off to integer. These integers are slope data.
L1G6-0 bits, L2G6-0 bits,
L3G6-0 bits, L4G6-0 bits
Slope Data
00H
0
(default)
01H
1
02H
2
:
:
7EH
126
7FH
127
Table 52. DVLC Slope Setting for Low Frequency Range
MS1402-E-06
- 90 -
2013/02