AK4679EG Datasheet, PDF (160/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
Addr
03H
Register Name
PLL Mode Select 0
R/W
Default
D7
D6
D5
D4
FS3
FS2
FS1
FS0
R/W
R/W
R/W
R/W
1
1
1
1
PLL3-0: PLL Reference Clock Select (Table 5)
Default: “0110” (MCKI pin, 12MHz)
FS3-0: Sampling Frequency Select (Table 6, Table 11 and Table 14)
Default: “1111” (fs=44.1kHz)
D3
PLL3
R/W
0
D2
PLL2
R/W
1
D1
PLL1
R/W
1
D0
PLL0
R/W
0
Addr
04H
Register Name
PLL Mode Select 1
R/W
Default
D7
D6
D5
D4
D3
CM1 CM0 BCKO
0
0
R/W R/W R/W
R
R
0
0
0
0
0
PMPLL: PLL Power Management
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
BCKO: BICK Output Frequency Select at Master Mode (Table 9)
CM1-0: MCKI Frequency Select at EXT Mode (Table 10 and Table 13)
Default: “00” (256fs)
D2
D1
D0
0
M/S PMPLL
R
R/W
R/W
0
0
0
Addr
05H
Register Name
Audio I/F Format Select
R/W
Default
D7
D6
0
0
R
R
0
0
D5
D4
D3
D2
D1
D0
0
SDOD MSBS BCKP
DIF1
DIF0
R
R/W R/W
R/W
R/W
R/W
0
0
0
0
1
0
DIF1-0: Audio Interface Format (Table 18)
Default: “10” (24bit Left justified)
BCKP: BICK Polarity at DSP Mode (Table 19)
“0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default)
“1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
MSBS: LRCK Phase at DSP Mode (Table 19)
“0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default)
“1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
SDOD: SDTO Disable (Table 83)
“0”: Enable (default)
“1”: Disable (“L”)
MS1402-E-06
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2013/02