AK4679EG Datasheet, PDF (143/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ Power-up Sequence and Device Setting
• Power-up, register setting, program download and RUN state sequence
The DSP must be in sleep state when downloading the program. Set DLRDY bit to “1” to power-up the internal
oscillation circuit, and after 100μs downloading becomes available. DLRDY bit must always be cleared when complete a
download. Then DSPTRSTN bit is cleared, the DSP block enters wait sync mode. In this state, CGU block is locked when
serial data clock input is detected and the DSP block becomes operating state.
Power supply
PDNE(pin)
PWSW bit
MRSTN bit
μP I/F
DLRDY bit
Glock Gen(int.)
DSPRSTN bit
0.6μs (min)
1μs (min)
Setting Register
100 μs(min)
Download DSP program
100 μs(min)
BCLKx,SYNCx pin
(x= 1 or 3)
Device state _{Power OFF}
Don’t care
Sleep State
Power Down Hardware Reset→Suspend
Input
Wait Sync Device Operational State
Figure 119. DSP Block Status
MS1402-E-06
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2013/02