AK4679EG Datasheet, PDF (159/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
Addr
01H
Register Name
Power Management 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
PMDAR PMDAL PMDRC PMEQ
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PMEQ: 5-band Parametric Equalizer Block Power Management
0: Power down (default)
1: Power up
PMDRC: Dynamic Range Control Block Power Management
0: Power down (default)
1: Power up
PMDAL: DAC Lch Power Management
0: Power down (default)
1: Power up
PMDAR: DAC Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDNA pin is “L”,
all blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value.
Addr
02H
Register Name
Power Management 1
R/W
Default
D7
D6
D5
ADRST
0
0
R/W
R
R
0
0
0
PMMP1: MPWR1 pin Power Management
0: Power down: Hi-Z (default)
1: Power up
MICL1: MIC Power (MPWR1 pin) Output Level select
Default “0”, typ. 2.5V (Table 22)
PMMP2: MPWR2 pin Power Management
0: Power down: Hi-Z (default)
1: Power up
MICL2: MIC Power (MPWR2 pin) Output Level Select
Default “0”, typ. 2.5V (Table 22)
ADRST: ADC Initialization Cycle Setting
0: 1059/fs (default)
1: 267/fs
D4
D3
D2
D1
D0
0
MICL2 PMMP2 MICL1 PMMP1
R
R/W
R/W
R/W
R/W
0
0
0
0
0
MS1402-E-06
- 159 -
2013/02