AK4679EG Datasheet, PDF (144/220 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679]
■ DSP State Transition (operational state ↔ wait sync)
Standby Sequence by SYNC1 and SYNC3
When SYNC input is stopped, fixed to “L” or “H” for more than 0.8ms during RUN state, CGU block is powered-down
and the DSP block enters the wait sync mode.
SYNC1 or SYNC3
CGU CTRL
>0.8ms
“H” or “L”
Device state Device Operational CGU unlocked
Wait Sync
Figure 120. Standby Sequence Example by SYNC1/3
Resume Sequence by SYNC1 and SYNC3
In wait sync mode, CGU block will be powered up in 5ms after SYNC1/3 input. The DSP block resumes operation when
DSP reset is released internally and the RAM data is cleared.
SYNC1 or SYNC3
“H” or “L”
< 5ms
CLKGEN & Ctrl
Device state
Wait Sync
CGU locked
Device Operational
Figure 121. Resume Sequence by SYNC1/3
Refer to Figure 118 for the sequence when resuming the operation from hardware default state.
MS1402-E-06
- 144 -
2013/02