Z80185 Datasheet, PDF (9/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
Ø
TOUT/DREQ
Timer Data
Reg = 0000H
47
Figure 8. Timer Output Timing
SLP Instruction Fetch
T3
T1
Ø
/INTi
T2
TS
TS
32
31
/NMI
A18-A0
/MREQ, /M1
/RD
/HALT
33
43
Figure 9. SLEEP Execution Cycle
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Next Opcode Fetch
T1
T2
44
DS971850301
9