Z80185 Datasheet, PDF (56/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Transmit Logic
Transmit FIFO
4 Bytes
Transmit MUX
Data Encoding & CRC
Generation
Receive and Transmit Clock Multipexer
Digital
Phase-Locked
Loop
Baud Rate
Generator
Crystal
Oscillator
Amplifier
Modem/Control Logic
Receive Logic
Rec. Status Rec. Data
FIFO 8-Byte FIFO 8-Byte
Receive MUX
SDLC Frame Status FIFO
10 x 19
CRC Checker,
Data Decode &
Sync Character
Detection
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
TxD
/TRxC
/RTxC
/CTS
/DCD
/RTS
/DTR
RxD
Databus
Control
CPU & DMA
Bus Interface
Interrupt
Control
/INT
/INTACK
IEI
IEO
Internal
Control
Logic
Interrupt
Control
Logic
Channel A
Register
Channel A
Tx-Rx
Figure 66. EMSCC Block Diagram
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DS971850301