Z80185 Datasheet, PDF (65/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
P1284 REGISTER MAP
Register Name
PARM Register
PARC Register
PARC2 Register
PART Register
PARV Register
I/O Addr/Access
(asymmetric)
%D9 R/W
%DA R/W
%DB WO
%DC R/W
%DD R/W
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER
The Centronics P1284 Controller can operate in either the
Host or Peripheral role in Compatibility mode (host to
printer), Nibble or Byte mode (printer to host), and ECP
mode (bidirectional). It provides no hardware support for
the EPP mode, although it may be possible to implement
this mode by software.
Nine control signals have dedicated hardware pins, and
have ± 12 mA drive (P1284 Level 2) capability as does the
8-bit data port PIA27-20. Note: Signal names listed below
are those for the original Compatible mode. The names
shown in parentheses represent the same signal, but in a
more recent mode. The Z80185 does not include hardware
support for the P1284 EPP mode.
The following signals are outputs in a Peripheral mode,
inputs in a Host mode:
s Busy (PtrBusy, PeriphAck)
s nAck (PtrClk, PeriphClk)
s PError (AckDataReq, nAckReverse)
s nFault (nDataAvail, nPeriphRequest)
s Select (Xflag)
The following signals are inputs in a Peripheral mode,
outputs in a Host mode:
s nStrobe (HostClk)
s nAutoFd (HostBusy, HostAck)
s nSelectIn (P1284Active)
s nInit (nReverseRequest)
Note that, because the Host/Peripheral mode is fully con-
trolled by software, a Z80185-based product can operate
as a Host in one system, or as a Peripheral in another,
without any change to the hardware. A Z80185-based
product could even act as a Host at one time and a
Peripheral at another time within the same system, if there
is a mechanism to control such alternate use.
In general, the interface architecture automates opera-
tions that are seen as performance-critical, while leaving
less frequent operations to software control. To achieve
top performance, software should assign a DMA channel
to the current direction of data flow.
Note: The IEEE 1284 Interface should be used with the
/IOC bit (bit D5) in the OMCR set to 0. The setting of this bit
primarily affects RLE expansion in peripheral ECP forward
and host ECP reverse modes.
DS971850301
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