Z80185 Datasheet, PDF (32/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
/M1
32K x 8 On-Chip Read-Only Memory (ROM)
The /M1 generation logic of the Z80180 allows the use of
logic analyzer disassemblers that rely on /M1 identifying
the start of each instruction. If the MIE bit is set to 1, the
processor does not refetch an RETI instruction.
Z80185 Counter/Timers
These facilities include two 16-bit Programmable Reload
Timers (PRTs) like those provided in the Z80180 and its
successors, plus four CTC channels like those in the
Z84C30. The TOUT output of PRT1 is output on a multi-
plexed pin, and the ZC/TO outputs and CLK/TRG inputs of
the CTC’s are multiplexed with PIA17-10 on an individual
basis, rather than simultaneously as on the Z80181. Inter-
nal cascading is provided between the CTCs, as de-
scribed in CTC Control section.
Z80185 I/O Chip Select
This output is active when an external master has control
of the bus, as well as when the Z80185 processor has
control. The /IOCS output of the Z80185 operates correctly
if the "180 registers" are relocated to I/O address 40-7F or
80-BF, and takes into account the "Decode High I/O" bit in
the Z80185 System Configuration Register.
The Z80185 processor features 32K x 8 of masked ROM.
This on-chip ROM allows zero-wait-state generation at the
maximum clock rate. The Z80195 processor is ROMless.
Z80185 On-Chip ROM Enable/Disable
If /WAIT is Low at the rising edge of /RESET, the on-chip
program memory is disabled and all accesses to ad-
dresses below the upper limit of /ROMCS go off-chip. This
feature allows code development and emulation using
external devices before the user is ready to use on-chip
memory.
If /WAIT is High at the rising edge of /RESET, accesses to
addresses below both the size of on-chip ROM and the
upper limit of /ROMCS, the user should select on-chip
ROM. Accesses that are above the size of the on-chip
ROM, but below the upper limit of /ROMCS, go off-chip with
/ROMCS asserted.
Power-Down
Modes
SLEEP
I/O STOP
SYSTEM STOP
IDLE^†
STANDBY^†
CPU
Core
Stop
Running
Stop
Stop
Stop
On-Chip
I/O
Running
Stop
Stop
Stop
Stop
Table 2. Power Down Modes
OSC.
Running
Running
Running
Running
Stop
CLKOUT
Running
Running
Running
Stop
Stop
Recovery
Source
RESET, Interrupts
By Programming
RESET, Interrupts
RESET, Interrupts, BUSREQ
RESET, Interrupts, BUSREQ
Recovery Time
(Minimum)
1.5 Clock
-
1.5 Clock
8 +1.5 Clock
2¹⁷ +1.5 Clock (Normal Recovery)
2⁶ +1.5 Clock (Quick Recovery)
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