Z80185 Datasheet, PDF (31/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185 MPU FUNCTIONAL DESCRIPTION (Continued)
Baud Rate Generator
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
The Baud Rate Generator (BRG) has two modes. The first
is the same as in the Z80180. The second is a 16-bit down
counter that divides the processor clock by the value in a
16-bit time constant register, and is identical to the EMSCC
BRG. This allows a common baud rate of up to 512 Kbps
to be selected. The BRG can also be disabled in favor of
an external clock on the CKA pin.
The Receiver and Transmitter will subsequently divide the
output of the BRG (or the signal from the CKA pin) by 1, 16
or 64, under the control of the DR bit in the CNTLB register,
and the X1 bit in the ASCI Extension Control Register. To
compute baud rate, use the following formulas.
If ss2,1,0 = 111, baud rate = f_CKA / Clock mode
else if BRG mode baud rate = f / (2 * (TC+2) * Clock
PHI
mode)
The ASCIs require a 50 percent duty cycle when CKA is
used as an input. Minimum High and Low times on CKA0
are typical of most CMOS devices.
RDRF is set, and if enabled an Rx Interrupt or DMA
Request is generated, when the receiver transfers a char-
acter from the Rx Shift Register to the Rx FIFO. The FIFO
merely provides margin against overruns. When there’s
more than one character in the FIFO, and software or a
DMA channel reads a character, RDRF either remains set
or is cleared and then immediately set again. For example,
if a receive interrupt service routine doesn’t read all the
characters in the RxFIFO, RDRF and the interrupt request
remain asserted.
The Rx DMA request is disabled when any of the error flags
PE or FE or OVRN are set, so that software can identify with
which character the problem is associated.
else baud rate = f / ((10 + 20*PS) * 2^ss * Clock mode)
PHI
Where:
BRG mode is bit 3 of the ASEXT register
PS is bit 5 of the CNTLB register
TC is the 16-bit value in the ASCI Time Constant registers
The TC value for a given baud rate is:
TC = (f / (2 * baud rate * Clock mode)) - 2
PHI
Clock mode depends on bit 4 in ASEXT and bit 3 in CNTLB:
X1 DR
Clock Mode
0
0 = 16
0
1 = 64
1
0 =1
1
1 = Reserved, do not use.
If Bit 7, RDRF Interrupt Inhibit, is set to 1 (see Figures 32
and 33), the ASCI does not request a Receive interrupt
when its RDRF flag is 1. Set this bit when programming a
DMA channel to handle the receive data from an ASCI. The
other causes for an ASCI Receive interrupt (PE, FE, OVRN,
and for ASCI0, DCD) continue to request Rx interrupt if the
RIE bit is 1. (The Rx DMA request is inhibited if PE or FE or
OVRN is set, so that software can tell where an error
occurred.) When this bit is 0, as it is after a Reset, RDRF will
cause an ASCI interrupt if RIE is 1.
Programmable Reload Timer (PRT)
This logic consists of two separate channels, each con-
taining a 16-bit counter (timer) and count reload register.
The time base for the counters is derived from the system
clock (divided by 20) before reaching the counter. PRT
channel 1 provides an optional output to allow for wave-
form generation.
2^ss depends on the three LS bits of the CNTLB register:
ss2 ss1 ss0
2^ss
0
0
0 =1
0
0
1 =2
0
1
0 =4
0
1
1 =8
1
0
0 = 16
1
0
1 = 32
1
1
0 = 64
1
1
1 = External Clock from CKA0
(see above).
The T output of PRT1 is available on a multiplexed pin.
OUT
Clocked Serial I/O (CSIO)
The pins for this function are multiplexed with the RTS,
CTS, and clock pins for ASCI0. Note: It is possible to use
both ASCI0 and the CSIO at the same time. If bit 4 of the
System Configuration Register is set to 1, the CKS clock
signal will internally drive the clock for ASCI0 instead of the
system clock.
DS971850301
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